Field of the Invention
The present disclosure relates to a three-dimensional integrated circuit capable of repairing failures in through-silicon vias.
Description of the Related Art
With the recent trend of high capacity, light weight and high density of electronic products, the operating voltage and size of electronic devices are also decreasing. The conventional planar two-dimensional mounting method has problems such as increase in package area due to increase in the number of I/O pads and slow signal transmission, and thus the method does not satisfy current trends in the electronics industry. Accordingly, three-dimensional packaging in which integrated circuits (ICs) are mounted by vertically stacking has been actively investigated. Recently, through-silicon via (TSV) technology of forming via holes in a silicon wafer and using the same as electrical paths has been attracting attention as one of methods described above.
However, various failures may be generated when the TSV technology is applied. For example, failures may include a void which is generated by incomplete filling of the inside of through-silicon vias (TSVs) with a conductive material in the process of forming TSVs, bump contact failure caused by bending of a semiconductor chip or movement of a bump material, a crack which occurs in a through-silicon via itself, and the like.
As described above, a TSV serves as a mediator for electrically connecting a plurality of semiconductor chips. Thus, when the TSV fails, the function thereof as an electrode cannot be normally exerted. In this case, a repair technique capable of replacing failed TSVs with normal TSVs is required.